A Hybrid of Bee Colony Optimization and Genetic Algorithm for Task Allocation in Multi-Core Systems to Minimize Makespan Igiri C. G Victor Peters Igu Ajumoke Elizabeth Volume 3, Issue 5, Pages 1-16, May 2026 Task scheduling in multi-core systems is a critical NP-hard optimization problem that significantly impacts system performance and resource utilization. This paper proposes a novel hybrid approach combining Bee Colony Optimization (BCO) and Genetic Algorithm (GA) for efficient task scheduling in multi-core processor systems. The hybrid BCO-GA algorithm leverages the global exploration capabil... Read More Article DOI: doi.org/10.47001/JAIET/2026.305001
Fault-Tolerant Task Scheduling in Multicore Systems Using Hybrid Metaheuristic Algorithms Adu, Folashade Christiana Igiri C.G Ogbolotuo Imumesen Solomon Ezekiel Cookey Volume 3, Issue 5, Pages 17-22, May 2026 Ensuring reliable and efficient task scheduling remains a critical challenge in multicore computing environments, particularly when system faults can significantly affect performance and interfere with execution. This paper presents a hybrid optimization strategy that combines Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) techniques to improve task allocation under fault-prone ... Read More Article DOI: doi.org/10.47001/JAIET/2026.305002
A Confidential Smart Tithe System with User-Controlled Giving and Local Assembly Redistribution Model Bassey Aniefiok Tom Davies Isobo Nelson Volume 3, Issue 5, Pages 23-33, May 2026 Traditional tithe management systems in religious institutions suffer from critical deficiencies in privacy protection, transparency, and equitable fund redistribution. This paper presents the Confidential Smart Tithe System (CSTS) which is a privacy-preserving, AI-augmented fintech platform designed to manage religious financial contributions with full donor anonymity, voluntary user-control... Read More Article DOI: doi.org/10.47001/JAIET/2026.305003
Adaptive Spotted Hyena Optimizer for Latency-Aware Task Scheduling in Heterogeneous Multicore Systems Igiri C. G. Ejekwu Obunezi Ujah Alechenu Israel Volume 3, Issue 5, Pages 34-52, May 2026 Heterogeneous multicore architectures encompassing Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Field-Programmable Gate Arrays (FPGAs) have emerged as the dominant computational paradigm for high-performance and embedded workloads. Task scheduling across such architectures presents a formidable challenge: the assignment of computational tasks to heterogeneous process... Read More Article DOI: doi.org/10.47001/JAIET/2026.305004
Design and Development of an ESP32-Based Speed Control System for Electric Bicycles Using a BTS7960 Motor Driver Christian Paul Navarro Francis Xavier Villanueva Volume 3, Issue 5, Pages 53-60, May 2026 This paper presents the design and development of an ESP32-based speed control system for an electric bicycle (E-Bike) using a BTS7960 motor driver. The proposed system employs a potentiometer as the user input device to regulate the motor speed through Pulse Width Modulation (PWM). Real-time operating parameters, including the calculated motor speed (RPM) and speed percentage, are displayed ... Read More Article DOI: doi.org/10.47001/JAIET/2026.305005
