Authors

Keerthana Rajeev

Electronics and Communication Engineering Department, IES College of Engineering, Thrissur-Kerala, India

Abstract

The Advanced High-performance Bus (AHB) protocol, defined under the ARM AMBA specification, is widely adopted in System-on-Chip (SoC) designs for high-speed communication between processors, memory controllers, and peripheral devices. Ensuring functional correctness and protocol compliance of AHB-based designs is critical due to increasing system complexity and stringent performance requirements. This paper presents the design and comprehensive verification of the AHB protocol using the Universal Verification Methodology (UVM) framework in SystemVerilog. The proposed verification environment is structured with reusable and scalable UVM components including drivers, monitors, sequencers, agents, scoreboards, and coverage collectors. AHB master and slave models are developed to validate transaction types such as single transfer, burst transfer, pipelined operations, and response handling mechanisms. Functional coverage metrics and constrained-random stimulus generation are employed to achieve exhaustive verification of address, data, and control signal interactions. Assertions are integrated to monitor protocol timing and handshaking requirements, ensuring compliance with AMBA specifications. Simulation results demonstrate effective bug detection, improved coverage closure, and enhanced verification efficiency compared to traditional directed testing approaches. The study highlights the advantages of UVM-based verification in achieving modularity, reusability, and scalability for complex bus protocol validation, making it suitable for modern SoC verification environments.

Keywords

Advanced High-performance Bus (AHB); AMBA Protocol; Universal Verification Methodology (UVM); SystemVerilog; Functional Verification

Citation of this Article

Keerthana Rajeev. (2025). Assertion-Based and Constrained Random Verification of AHB Protocol Using UVM. Journal of Artificial Intelligence and Emerging Technologies (JAIET). 2(2), 22-25. Article DOI: https://doi.org/10.47001/JAIET/2025.202005

Licence Copyright (c) 2026 Journal of Artificial Intelligence and Emerging Technologies. This work is licensed under a Creative Commons Attribution Non Commercial 4.0 International Licence.

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